As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any liner/barrier metals) is deposited, patterned, and etched to form the interconnect lines. Then, a dielectric is deposited and planarized. In a damascene process, the dielectric is formed first. The dielectric is then patterned and etched. A thin liner/barrier material is then deposited over the structure followed by copper deposition over the liner/barrier material. Then, the copper and liner/barrier material are chemically-mechanically polished to remove the material from over the dielectric, leaving metal interconnect lines. A metal etch is thereby avoided.
The most practical technique for forming copper interconnects is electrochemical deposition (ECD). In this process, after the liner/barrier material is deposited, a seed layer of copper is deposited. Then, ECD is used to deposit copper over the seed layer. Unfortunately, physical vapor deposition (PVD) processes typically used to deposit the liner/barrier and seed materials have poor step coverage. This is due to the fact that PVD processes use a line of sight technique. As a result, an overhang of the liner/barrier and/or seed material occurs at the top of a trench or via. The overhang causes a severe problem during the subsequent copper ECD. Specifically, a seam can occur in the copper fill material.
One proposed solution for overcoming the above problem uses a pre-sputter etch after the trench and via or contact etch, but before liner/barrier deposition. Unfortunately, the sputter etch step can deposit copper onto the sidewalls. Copper can then diffuse through the dielectric and cause reliability problems. Also, the use of a pre-sputter etch can lead to faceting/corner rounding of the features, making the adjacent structures more prone to electrical leakage due to a reduction of line-to-line separation distance.